Author | Wouter van Ooijen, Copyright (C) 1998, 1999 Wouter van Ooijen |
Adapted-by | Joep Suijs. |
Compiler | >=2.4g |
Software implementation of I2C (single) master.
i2c_initialize()
i2c_initialize - initialize the software i2c bus The output latch values are always low, the lines are switched open-collector fashion by manipulating the direction registers.
i2c_stop()
i2c_stop - output a stop condition
i2c_start()
i2c_start - output a start condition
i2c_restart()
i2c_restart - output a (re)start condition A restart is a start without a previous stop. This procedure is provided as part of the API to maintain compatibility with the i2c hardware master lib.
_i2c_bit_out(bit in x)
_i2c_bit_out- output a single bit (for internal use only)
_i2c_bit_in(bit out x)
_i2c_bit_in- input a single bit (for internal use only)
_i2c_wait()
_i2c_wait - wait for a change to settle (for internal use only) The delay is determined by i2c_bus_speed and is 1/4 of the cycle time. Given the delay resolution of 1 us and all actions required by i2c_software routines, the actual bus speed will be lower then the configured maximum.
i2c_receive_byte( bit in ack) return byte
i2c_receive_byte - read one byte The ACK flag indicated if the byte read must be acked. In general, all bytes read by the master are acked, except the last one. Failing to NACK the last byte read will give unpredictable results. (Often it will provide repeatable sequences, where one out of 2 to 4 of the reads from a specific device is correct. You are warned!)
i2c_transmit_byte( byte in x ) return bit
i2c_transmit_byte - output one byte
16f648a | 16f648a_i2c_sw_l1.jal |
16f877a | 16f877a_i2c_sw_l1.jal |
16f877a | 16f877a_i2c_sw_master_check_bus.jal |
16f877a | 16f877a_i2c_sw_master_echo.jal |
16f88 | 16f88_i2c_sw_master_echo.jal |
16f88 | 16f88_i2c_sw_master_check_bus.jal |
16f88 | 16f88_i2c_sw_l1.jal |
18f14k50 | 18f14k50_i2c_sw_master_check_bus.jal |
18f14k50 | 18f14k50_i2c_sw_master_echo.jal |
18f14k50 | 18f14k50_i2c_sw_l1.jal |
18f2450 | 18f2450_i2c_sw_master_echo.jal |
18f2450 | 18f2450_i2c_sw_l1.jal |
18f2450 | 18f2450_i2c_sw_master_check_bus.jal |
18f4550 | 18f4550_i2c_sw_master_echo.jal |
18f4550 | 18f4550_i2c_sw_master_check_bus.jal |
18f4550 | 18f4550_i2c_sw_l1.jal |