# enc28j60

Ethernet Device ENC28j60

Author | Matthew Schinkel - borntechi.com, copyright © 2011, all rights reserved.
Adapted-by |
Compiler | >=2.4n

Description

    controls the ehernet device ENC28j60 for networking.

Sources

    http://www.microchip.com/wwwproducts/Devices.aspx?dDocName=en022889
    enc28j60 C library by Pascal Stang
    enc28j60 C library by Guido Socher

Dependencies

- delay

## Summary

### Global variables/contants

- `const ERXNDL = (0x0A|ENC_BANK_0)`
- `const PHCON2_FRCLINK = 0x4000`
- `const EDMADSTH = (0x15|ENC_BANK_0)`
- `const MISTAT = (0x0A|ENC_BANK_3|ENC_MIL)`
- `const EPAUSH = (0x19|ENC_BANK_3)`
- `const MABBIPG = (0x04|ENC_BANK_2|ENC_MAC)`
- `const EIR_WOLIF = 0x04`
- `const EIE_INTIE = 0x80`
- `const EPMM3 = (0x0B|ENC_BANK_1)`
- `const EIR_DMAIF = 0x20`
- `const EPMM7 = (0x0F|ENC_BANK_1)`
- `const MACON2_RFUNRST = 0x04`
- `const EHT0 = (0x00|ENC_BANK_1)`
- `const MAADR4 = (0x05|ENC_BANK_3|ENC_MAC)`
- `const EIR_PKTIF = 0x40`
- `const MISTAT_BUSY = 0x01`
- `const EDMACSL = (0x16|ENC_BANK_0)`
- `const PHCON1_PPWRSV = 0x0800`
- `const EPMCSH = (0x11|ENC_BANK_1)`
- `const EHT7 = (0x07|ENC_BANK_1)`
- `const MACON1_TXPAUS = 0x08`
- `const ETXNDH = (0x07|ENC_BANK_0)`
- `const ERXFCON_MPEN = 0x08`
- `const EIR = 0x1C`
- `const PHCON2 = 0x10`
- `const MACON2_MATXRST = 0x02`
- `const ECON2 = 0x1E`
- `const ENC_DISABLE = 0`
- `const EIE_PKTIE = 0x40`
- `const ESTAT_RXBUSY = 0x04`
- `const MIRDL = (0x18|ENC_BANK_2|ENC_MIL)`
- `const MACON1_MARXEN = 0x01`
- `const EHT6 = (0x06|ENC_BANK_1)`
- `const MACON2 = (0x01|ENC_BANK_2|ENC_MAC)`
- `const PHHID2 = 0x03`
- `const byte ENC_MAX_FRAMELEN_H = 0x05`
- `const EIR_TXERIF = 0x02`
- `const ENC_BANK_3 = 0x60`
- `const EIE_LINKIE = 0x10`
- `const ECOCON = (0x15|ENC_BANK_3)`
- `const EDMASTH = (0x11|ENC_BANK_0)`
- `const EPMM5 = (0x0D|ENC_BANK_1)`
- `var byte enc_current_bank`
- `const ENC28J60_READ_CTRL_REG = 0x00`
- `const ENC_BANK_2 = 0x40`
- `const ERXFCON = (0x18|ENC_BANK_1)`
- `var byte _enc_packet_pointer[2] at enc_packet_pointer`
- `const MICON = (0x11|ENC_BANK_2|ENC_MIL)`
- `const EHT1 = (0x01|ENC_BANK_1)`
- `const ERXSTH = (0x09|ENC_BANK_0)`
- `const EDMANDL = (0x12|ENC_BANK_0)`
- `const EIE = 0x1B`
- `const MACLCON2 = (0x09|ENC_BANK_2|ENC_MAC)`
- `const MACON1_RXPAUS = 0x04`
- `const ERXWRPTH = (0x0F|ENC_BANK_0)`
- `const ERXNDH = (0x0B|ENC_BANK_0)`
- `const ENC28J60_BIT_CLEAR = 0xA0`
- `const ERXFCON_CRCEN = 0x20`
- `const byte RXSTOP_INIT_L = 0xFE`
- `const MACON3_PADCFG0 = 0x20`
- `const ETXSTL = (0x04|ENC_BANK_0)`
- `const EPMCSL = (0x10|ENC_BANK_1)`
- `const EDMADSTL = (0x14|ENC_BANK_0)`
- `const SPRD_MASK = 0x80`
- `const PHCON1_PDPXMD = 0x0100`
- `const EWOLIR = (0x17|ENC_BANK_1)`
- `const MACLCON1 = (0x08|ENC_BANK_2|ENC_MAC)`
- `const PHSTAT1_JBSTAT = 0x0002`
- `const MACON3_FULDPX = 0x01`
- `const ERXFCON_HTEN = 0x04`
- `const MAADR5 = (0x04|ENC_BANK_3|ENC_MAC)`
- `const ECON2_VRPS = 0x08`
- `const ENC_MIL = 0x80`
- `const ESTAT_TXABRT = 0x02`
- `const ECON1_BSEL0 = 0x01`
- `const PHSTAT1_PFDPX = 0x1000`
- `const EREVID = (0x12|ENC_BANK_3)`
- `const ENC_8_333 = 3`
- `const PHCON2_HDLDIS = 0x0100`
- `const ERXWRPTL = (0x0E|ENC_BANK_0)`
- `const MISTAT_NVALID = 0x04`
- `const MACON1 = (0x00|ENC_BANK_2|ENC_MAC)`
- `var word enc_packet_pointer = 0`
- `const ERXRDPTH = (0x0D|ENC_BANK_0)`
- `const EHT2 = (0x02|ENC_BANK_1)`
- `const EPMM6 = (0x0E|ENC_BANK_1)`
- `const MAADR0 = (0x01|ENC_BANK_3|ENC_MAC)`
- `const PHHID1 = 0x02`
- `const word RXSTOP_INIT = (0x1FFF-0x0600-1)`
- `const ENC_25 = 1`
- `const ENC_MAC = 0x80`
- `const MICMD_MIIRD = 0x01`
- `const EDMACSH = (0x17|ENC_BANK_0 )`
- `const EPMM1 = (0x09|ENC_BANK_1)`
- `const PHLCON = 0x14`
- `const MIWRL = (0x16|ENC_BANK_2|ENC_MIL)`
- `const MACON2_MARST = 0x80`
- `const word ENC_MAX_FRAMELEN = 1500`
- `const ENC_BANK_0 = 0x00`
- `const PHSTAT1_LLSTAT = 0x0004`
- `const MAADR3 = (0x02|ENC_BANK_3|ENC_MAC)`
- `const ENC_3_125 = 5`
- `const EPKTCNT = (0x19|ENC_BANK_1)`
- `const EPMM2 = (0x0A|ENC_BANK_1)`
- `const ECON2_PWRSV = 0x20`
- `const PHSTAT2 = 0x11`
- `const MAIPGL = (0x06|ENC_BANK_2|ENC_MAC)`
- `const MACON1_LOOPBK = 0x10`
- `const EPAUSL = (0x18|ENC_BANK_3)`
- `const EPMM4 = (0x0C|ENC_BANK_1)`
- `const EIR_TXIF = 0x08`
- `const MACON1_PASSALL = 0x02`
- `const ENC_12_5 = 2`
- `const ERXSTL = (0x08|ENC_BANK_0)`
- `const EBSTSD = (0x06|ENC_BANK_3)`
- `const ETXNDL = (0x06|ENC_BANK_0)`
- `const PKTCTRL_POVERRIDE = 0x01`
- `const ECON1_RXEN = 0x04`
- `const EBSTCSH = (0x09|ENC_BANK_3)`
- `const EBSTCON = (0x07|ENC_BANK_3)`
- `const ERXFCON_ANDOR = 0x40`
- `const word TXSTOP_INIT = 0x1FFF`
- `const EIE_WOLIE = 0x04`
- `const MACON4 = (0x03|ENC_BANK_2|ENC_MAC)`
- `const PKTCTRL_PCRCEN = 0x02`
- `const ENC28J60_BIT_SET = 0x80`
- `const EPMOL = (0x14|ENC_BANK_1)`
- `const EHT4 = (0x04|ENC_BANK_1)`
- `const ADDR_MASK = 0x1F`
- `const byte ENC_MAX_FRAMELEN_L = 0xDC`
- `const ECON2_PKTDEC = 0x40`
- `const PHIE = 0x12`
- `const byte RXSTOP_INIT_H = 0x19`
- `const MAPHSUP = (0x0D|ENC_BANK_2|ENC_MAC)`
- `const ENC_BANK_1 = 0x20`
- `const ENC_6_25 = 4`
- `const byte TXSTOP_INIT_H = 0x1F`
- `const PHCON1_PRST = 0x8000`
- `const EWRPTH = (0x03|ENC_BANK_0)`
- `const MACON3_PADCFG2 = 0x80`
- `const MACON3_FRMLNEN = 0x02`
- `const MAIPGH = (0x07|ENC_BANK_2|ENC_MAC)`
- `const MACON3 = (0x02|ENC_BANK_2|ENC_MAC)`
- `const EWRPTL = (0x02|ENC_BANK_0)`
- `const EIR_LINKIF = 0x10`
- `const ESTAT_LATECOL = 0x10`
- `const MACON3_PHDRLEN = 0x08`
- `const EHT5 = (0x05|ENC_BANK_1)`
- `const MAMXFLL = (0x0A|ENC_BANK_2|ENC_MAC)`
- `const MIREGADR = (0x14|ENC_BANK_2|ENC_MIL)`
- `const MACON2_RNDRST = 0x40`
- `const MISTAT_SCAN = 0x02`
- `const MICMD_MIISCAN = 0x02`
- `const MAADR1 = (0x00|ENC_BANK_3|ENC_MAC)`
- `const EIR_RXERIF = 0x01`
- `const MACON3_TXCRCEN = 0x10`
- `const PKTCTRL_PPADEN = 0x04`
- `const ECON1_RXRST = 0x40`
- `const ERXRDPTL = (0x0C|ENC_BANK_0)`
- `const EWOLIE = (0x16|ENC_BANK_1)`
- `const ENC28J60_WRITE_CTRL_REG = 0x40`
- `const ECON1_CSUMEN = 0x10`
- `const ERXFCON_PMEN = 0x10`
- `const EHT3 = (0x03|ENC_BANK_1)`
- `const word TXSTART_INIT = (0x1FFF-0x0600)`
- `const EPMM0 = (0x08|ENC_BANK_1)`
- `const ESTAT = 0x1D`
- `const ECON1_BSEL1 = 0x02`
- `const EDMANDH = (0x13|ENC_BANK_0)`
- `const MIRDH = (0x19|ENC_BANK_2|ENC_MIL)`
- `const EFLOCON = (0x17|ENC_BANK_3)`
- `const ERXFCON_UCEN = 0x80`
- `const EBSTCSL = (0x08|ENC_BANK_3)`
- `const PHSTAT1 = 0x01`
- `const BANK_MASK = 0x60`
- `const PHCON2_TXDIS = 0x2000`
- `const ECON1 = 0x1F`
- `const ERDPTL = (0x00|ENC_BANK_0)`
- `const ECON1_TXRST = 0x80`
- `const ENC28J60_WRITE_BUF_MEM = 0x7A`
- `const MAADR2 = (0x03|ENC_BANK_3|ENC_MAC)`
- `const PKTCTRL_PHUGEEN = 0x08`
- `const MACON2_TFUNRST = 0x01`
- `const MAMXFLH = (0x0B|ENC_BANK_2|ENC_MAC)`
- `const ECON1_DMAST = 0x20`
- `const EIE_TXERIE = 0x02`
- `const EDMASTL = (0x10|ENC_BANK_0)`
- `const ERXFCON_BCEN = 0x01`
- `const EPMOH = (0x15|ENC_BANK_1)`
- `const byte TXSTART_INIT_H = 0x19`
- `const PHCON1 = 0x00`
- `const MIWRH = (0x17|ENC_BANK_2|ENC_MIL)`
- `const ECON2_AUTOINC = 0x80`
- `const EIE_TXIE = 0x08`
- `const EIE_RXERIE = 0x01`
- `const ENC28J60_SOFT_RESET = 0xFF`
- `const byte TXSTOP_INIT_L = 0xFF`
- `const byte TXSTART_INIT_L = 0xFF`
- `const PHSTAT1_PHDPX = 0x0800`
- `const ETXSTH = (0x05|ENC_BANK_0)`
- `const ENC28J60_READ_BUF_MEM = 0x3A`
- `const EIE_DMAIE = 0x20`
- `const MACON2_MARXRST = 0x08`
- `const ERXFCON_MCEN = 0x02`
- `const ESTAT_CLKRDY = 0x01`
- `const ERDPTH = (0x01|ENC_BANK_0)`
- `const PHCON2_JABBER = 0x0400`
- `const MACON3_HFRMLEN = 0x04`
- `const ECON1_TXRTS = 0x08`
- `const PHCON1_PLOOPBK = 0x4000`
- `const MACON3_PADCFG1 = 0x40`
- `const PHIR = 0x13`
- `const MICMD = (0x12|ENC_BANK_2|ENC_MIL)`
- `const ESTAT_INT = 0x80`

### Procedures

- `enc_clear_rx_buffer()`
- `enc_write_buffer(word in len)`
- `enc_complete_packet_read()`
- `enc_end_packet(word in network_current_packet_size)`
- `enc_set_bank(byte in address)`
- `enc_set_clkout_freq(byte in clk)`
- `enc_write_phy_register(byte in address, word in data)`
- `enc_read_buffer(word in len)`
- `enc_init()`
- `enc_spi_write_command(byte in operation, byte in address, byte in data)`
- `enc_write_register(byte in address, byte in data)`

### Functions

- `enc_packet_size'get() return word`
- `enc_read_revision() return byte`
- `enc_packets_available() return byte`
- `enc_packet_available'get() return bit`
- `enc_spi_read_command(byte in operation, byte in address) return byte`
- `enc_read_register(byte in address) return byte`

## API details

### Global variables/contants

- `const ERXNDL = (0x0A|ENC_BANK_0)`

  No documentation found

- `const PHCON2_FRCLINK = 0x4000`

      ENC28J60 PHY PHCON2 Register Bit Definitions

- `const EDMADSTH = (0x15|ENC_BANK_0)`

  No documentation found

- `const MISTAT = (0x0A|ENC_BANK_3|ENC_MIL)`

  No documentation found

- `const EPAUSH = (0x19|ENC_BANK_3)`

  No documentation found

- `const MABBIPG = (0x04|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const EIR_WOLIF = 0x04`

  No documentation found

- `const EIE_INTIE = 0x80`

      ENC28J60 EIE Register Bit Definitions

- `const EPMM3 = (0x0B|ENC_BANK_1)`

  No documentation found

- `const EIR_DMAIF = 0x20`

  No documentation found

- `const EPMM7 = (0x0F|ENC_BANK_1)`

  No documentation found

- `const MACON2_RFUNRST = 0x04`

  No documentation found

- `const EHT0 = (0x00|ENC_BANK_1)`

      Bank 1 registers

- `const MAADR4 = (0x05|ENC_BANK_3|ENC_MAC)`

  No documentation found

- `const EIR_PKTIF = 0x40`

      ENC28J60 EIR Register Bit Definitions

- `const MISTAT_BUSY = 0x01`

  No documentation found

- `const EDMACSL = (0x16|ENC_BANK_0)`

  No documentation found

- `const PHCON1_PPWRSV = 0x0800`

  No documentation found

- `const EPMCSH = (0x11|ENC_BANK_1)`

  No documentation found

- `const EHT7 = (0x07|ENC_BANK_1)`

  No documentation found

- `const MACON1_TXPAUS = 0x08`

  No documentation found

- `const ETXNDH = (0x07|ENC_BANK_0)`

  No documentation found

- `const ERXFCON_MPEN = 0x08`

  No documentation found

- `const EIR = 0x1C`

  No documentation found

- `const PHCON2 = 0x10`

  No documentation found

- `const MACON2_MATXRST = 0x02`

  No documentation found

- `const ECON2 = 0x1E`

  No documentation found

- `const ENC_DISABLE = 0`

  No documentation found

- `const EIE_PKTIE = 0x40`

  No documentation found

- `const ESTAT_RXBUSY = 0x04`

  No documentation found

- `const MIRDL = (0x18|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const MACON1_MARXEN = 0x01`

  No documentation found

- `const EHT6 = (0x06|ENC_BANK_1)`

  No documentation found

- `const MACON2 = (0x01|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const PHHID2 = 0x03`

  No documentation found

- `const byte ENC_MAX_FRAMELEN_H = 0x05`

  No documentation found

- `const EIR_TXERIF = 0x02`

  No documentation found

- `const ENC_BANK_3 = 0x60`

  No documentation found

- `const EIE_LINKIE = 0x10`

  No documentation found

- `const ECOCON = (0x15|ENC_BANK_3)`

  No documentation found

- `const EDMASTH = (0x11|ENC_BANK_0)`

  No documentation found

- `const EPMM5 = (0x0D|ENC_BANK_1)`

  No documentation found

- `var byte enc_current_bank`

  No documentation found

- `const ENC28J60_READ_CTRL_REG = 0x00`

      Registers for spi interface control

- `const ENC_BANK_2 = 0x40`

  No documentation found

- `const ERXFCON = (0x18|ENC_BANK_1)`

  No documentation found

- `var byte _enc_packet_pointer[2] at enc_packet_pointer`

  No documentation found

- `const MICON = (0x11|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const EHT1 = (0x01|ENC_BANK_1)`

  No documentation found

- `const ERXSTH = (0x09|ENC_BANK_0)`

  No documentation found

- `const EDMANDL = (0x12|ENC_BANK_0)`

  No documentation found

- `const EIE = 0x1B`

      Registers located in all banks

- `const MACLCON2 = (0x09|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const MACON1_RXPAUS = 0x04`

  No documentation found

- `const ERXWRPTH = (0x0F|ENC_BANK_0)`

  No documentation found

- `const ERXNDH = (0x0B|ENC_BANK_0)`

  No documentation found

- `const ENC28J60_BIT_CLEAR = 0xA0`

  No documentation found

- `const ERXFCON_CRCEN = 0x20`

  No documentation found

- `const byte RXSTOP_INIT_L = 0xFE`

  No documentation found

- `const MACON3_PADCFG0 = 0x20`

  No documentation found

- `const ETXSTL = (0x04|ENC_BANK_0)`

  No documentation found

- `const EPMCSL = (0x10|ENC_BANK_1)`

  No documentation found

- `const EDMADSTL = (0x14|ENC_BANK_0)`

  No documentation found

- `const SPRD_MASK = 0x80`

  No documentation found

- `const PHCON1_PDPXMD = 0x0100`

  No documentation found

- `const EWOLIR = (0x17|ENC_BANK_1)`

  No documentation found

- `const MACLCON1 = (0x08|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const PHSTAT1_JBSTAT = 0x0002`

  No documentation found

- `const MACON3_FULDPX = 0x01`

  No documentation found

- `const ERXFCON_HTEN = 0x04`

  No documentation found

- `const MAADR5 = (0x04|ENC_BANK_3|ENC_MAC)`

  No documentation found

- `const ECON2_VRPS = 0x08`

  No documentation found

- `const ENC_MIL = 0x80`

  No documentation found

- `const ESTAT_TXABRT = 0x02`

  No documentation found

- `const ECON1_BSEL0 = 0x01`

  No documentation found

- `const PHSTAT1_PFDPX = 0x1000`

      ENC28J60 PHY PHSTAT1 Register Bit Definitions

- `const EREVID = (0x12|ENC_BANK_3)`

  No documentation found

- `const ENC_8_333 = 3`

  No documentation found

- `const PHCON2_HDLDIS = 0x0100`

  No documentation found

- `const ERXWRPTL = (0x0E|ENC_BANK_0)`

  No documentation found

- `const MISTAT_NVALID = 0x04`

      ENC28J60 MISTAT Register Bit Definitions

- `const MACON1 = (0x00|ENC_BANK_2|ENC_MAC)`

      Bank 2 registers

- `var word enc_packet_pointer = 0`

  No documentation found

- `const ERXRDPTH = (0x0D|ENC_BANK_0)`

  No documentation found

- `const EHT2 = (0x02|ENC_BANK_1)`

  No documentation found

- `const EPMM6 = (0x0E|ENC_BANK_1)`

  No documentation found

- `const MAADR0 = (0x01|ENC_BANK_3|ENC_MAC)`

  No documentation found

- `const PHHID1 = 0x02`

  No documentation found

- `const word RXSTOP_INIT = (0x1FFF-0x0600-1)`

      receive buffer end

- `const ENC_25 = 1`

  No documentation found

- `const ENC_MAC = 0x80`

  No documentation found

- `const MICMD_MIIRD = 0x01`

  No documentation found

- `const EDMACSH = (0x17|ENC_BANK_0 )`

  No documentation found

- `const EPMM1 = (0x09|ENC_BANK_1)`

  No documentation found

- `const PHLCON = 0x14`

  No documentation found

- `const MIWRL = (0x16|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const MACON2_MARST = 0x80`

      ENC28J60 MACON2 Register Bit Definitions

- `const word ENC_MAX_FRAMELEN = 1500`

      max frame length which the conroller will accept:
      maximum ethernet frame length would be 1518??

- `const ENC_BANK_0 = 0x00`

      banks

- `const PHSTAT1_LLSTAT = 0x0004`

  No documentation found

- `const MAADR3 = (0x02|ENC_BANK_3|ENC_MAC)`

  No documentation found

- `const ENC_3_125 = 5`

      set clkout pin frequency
      0b11x = Reserved for factory test. Do not use. Glitch prevention not assured.
      5 = CLKOUT outputs main clock divided by 8 (3.125 MHz)
      4 = CLKOUT outputs main clock divided by 4 (6.25 MHz)
      3 = CLKOUT outputs main clock divided by 3 (8.333333 MHz)
      2 = CLKOUT outputs main clock divided by 2 (12.5 MHz)
      1 = CLKOUT outputs main clock divided by 1 (25 MHz)
      0 = CLKOUT is disabled. The pin is driven low.

- `const EPKTCNT = (0x19|ENC_BANK_1)`

  No documentation found

- `const EPMM2 = (0x0A|ENC_BANK_1)`

  No documentation found

- `const ECON2_PWRSV = 0x20`

  No documentation found

- `const PHSTAT2 = 0x11`

  No documentation found

- `const MAIPGL = (0x06|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const MACON1_LOOPBK = 0x10`

      ENC28J60 MACON1 Reg=ister Bit Definitions

- `const EPAUSL = (0x18|ENC_BANK_3)`

  No documentation found

- `const EPMM4 = (0x0C|ENC_BANK_1)`

  No documentation found

- `const EIR_TXIF = 0x08`

  No documentation found

- `const MACON1_PASSALL = 0x02`

  No documentation found

- `const ENC_12_5 = 2`

  No documentation found

- `const ERXSTL = (0x08|ENC_BANK_0)`

  No documentation found

- `const EBSTSD = (0x06|ENC_BANK_3)`

  No documentation found

- `const ETXNDL = (0x06|ENC_BANK_0)`

  No documentation found

- `const PKTCTRL_POVERRIDE = 0x01`

  No documentation found

- `const ECON1_RXEN = 0x04`

  No documentation found

- `const EBSTCSH = (0x09|ENC_BANK_3)`

  No documentation found

- `const EBSTCON = (0x07|ENC_BANK_3)`

  No documentation found

- `const ERXFCON_ANDOR = 0x40`

  No documentation found

- `const word TXSTOP_INIT = 0x1FFF`

      stp TX buffer at end of mem

- `const EIE_WOLIE = 0x04`

  No documentation found

- `const MACON4 = (0x03|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const PKTCTRL_PCRCEN = 0x02`

  No documentation found

- `const ENC28J60_BIT_SET = 0x80`

  No documentation found

- `const EPMOL = (0x14|ENC_BANK_1)`

  No documentation found

- `const EHT4 = (0x04|ENC_BANK_1)`

  No documentation found

- `const ADDR_MASK = 0x1F`

      ENC28J60 Control Registers
      Control register definitions are a combination of address,
      bank number, and Ethernet/MAC/PHY indicator bits.
      Register address  (bits 0-4)
      Bank number       (bits 5-6)
      MAC/PHY indicator (bit 7)
      Bit masks

- `const byte ENC_MAX_FRAMELEN_L = 0xDC`

  No documentation found

- `const ECON2_PKTDEC = 0x40`

  No documentation found

- `const PHIE = 0x12`

  No documentation found

- `const byte RXSTOP_INIT_H = 0x19`

  No documentation found

- `const MAPHSUP = (0x0D|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const ENC_BANK_1 = 0x20`

  No documentation found

- `const ENC_6_25 = 4`

  No documentation found

- `const byte TXSTOP_INIT_H = 0x1F`

  No documentation found

- `const PHCON1_PRST = 0x8000`

      ENC28J60 PHY PHCON1 Register Bit Definitions

- `const EWRPTH = (0x03|ENC_BANK_0)`

  No documentation found

- `const MACON3_PADCFG2 = 0x80`

      ENC28J60 MACON3 Register Bit Definitions

- `const MACON3_FRMLNEN = 0x02`

  No documentation found

- `const MAIPGH = (0x07|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const MACON3 = (0x02|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const EWRPTL = (0x02|ENC_BANK_0)`

  No documentation found

- `const EIR_LINKIF = 0x10`

  No documentation found

- `const ESTAT_LATECOL = 0x10`

  No documentation found

- `const MACON3_PHDRLEN = 0x08`

  No documentation found

- `const EHT5 = (0x05|ENC_BANK_1)`

  No documentation found

- `const MAMXFLL = (0x0A|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const MIREGADR = (0x14|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const MACON2_RNDRST = 0x40`

  No documentation found

- `const MISTAT_SCAN = 0x02`

  No documentation found

- `const MICMD_MIISCAN = 0x02`

      ENC28J60 MICMD Register Bit Definitions

- `const MAADR1 = (0x00|ENC_BANK_3|ENC_MAC)`

      Bank 3 registers

- `const EIR_RXERIF = 0x01`

  No documentation found

- `const MACON3_TXCRCEN = 0x10`

  No documentation found

- `const PKTCTRL_PPADEN = 0x04`

  No documentation found

- `const ECON1_RXRST = 0x40`

  No documentation found

- `const ERXRDPTL = (0x0C|ENC_BANK_0)`

  No documentation found

- `const EWOLIE = (0x16|ENC_BANK_1)`

  No documentation found

- `const ENC28J60_WRITE_CTRL_REG = 0x40`

  No documentation found

- `const ECON1_CSUMEN = 0x10`

  No documentation found

- `const ERXFCON_PMEN = 0x10`

  No documentation found

- `const EHT3 = (0x03|ENC_BANK_1)`

  No documentation found

- `const word TXSTART_INIT = (0x1FFF-0x0600)`

      start TX buffer at 0x1FFF-0x0600, place for one full ethernet frame (~1500 bytes)

- `const EPMM0 = (0x08|ENC_BANK_1)`

  No documentation found

- `const ESTAT = 0x1D`

  No documentation found

- `const ECON1_BSEL1 = 0x02`

  No documentation found

- `const EDMANDH = (0x13|ENC_BANK_0)`

  No documentation found

- `const MIRDH = (0x19|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const EFLOCON = (0x17|ENC_BANK_3)`

  No documentation found

- `const ERXFCON_UCEN = 0x80`

      ENC28J60 ERXFCON Register Bit Definitions

- `const EBSTCSL = (0x08|ENC_BANK_3)`

  No documentation found

- `const PHSTAT1 = 0x01`

  No documentation found

- `const BANK_MASK = 0x60`

  No documentation found

- `const PHCON2_TXDIS = 0x2000`

  No documentation found

- `const ECON1 = 0x1F`

  No documentation found

- `const ERDPTL = (0x00|ENC_BANK_0)`

      Bank 0 registers

- `const ECON1_TXRST = 0x80`

      ENC28J60 ECON1 Register Bit Definitions

- `const ENC28J60_WRITE_BUF_MEM = 0x7A`

  No documentation found

- `const MAADR2 = (0x03|ENC_BANK_3|ENC_MAC)`

  No documentation found

- `const PKTCTRL_PHUGEEN = 0x08`

      ENC28J60 Packet Control Byte Bit Definitions

- `const MACON2_TFUNRST = 0x01`

  No documentation found

- `const MAMXFLH = (0x0B|ENC_BANK_2|ENC_MAC)`

  No documentation found

- `const ECON1_DMAST = 0x20`

  No documentation found

- `const EIE_TXERIE = 0x02`

  No documentation found

- `const EDMASTL = (0x10|ENC_BANK_0)`

  No documentation found

- `const ERXFCON_BCEN = 0x01`

  No documentation found

- `const EPMOH = (0x15|ENC_BANK_1)`

  No documentation found

- `const byte TXSTART_INIT_H = 0x19`

  No documentation found

- `const PHCON1 = 0x00`

      PHY registers

- `const MIWRH = (0x17|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const ECON2_AUTOINC = 0x80`

      ENC28J60 ECON2 Register Bit Definitions

- `const EIE_TXIE = 0x08`

  No documentation found

- `const EIE_RXERIE = 0x01`

  No documentation found

- `const ENC28J60_SOFT_RESET = 0xFF`

  No documentation found

- `const byte TXSTOP_INIT_L = 0xFF`

  No documentation found

- `const byte TXSTART_INIT_L = 0xFF`

  No documentation found

- `const PHSTAT1_PHDPX = 0x0800`

  No documentation found

- `const ETXSTH = (0x05|ENC_BANK_0)`

  No documentation found

- `const ENC28J60_READ_BUF_MEM = 0x3A`

  No documentation found

- `const EIE_DMAIE = 0x20`

  No documentation found

- `const MACON2_MARXRST = 0x08`

  No documentation found

- `const ERXFCON_MCEN = 0x02`

  No documentation found

- `const ESTAT_CLKRDY = 0x01`

  No documentation found

- `const ERDPTH = (0x01|ENC_BANK_0)`

  No documentation found

- `const PHCON2_JABBER = 0x0400`

  No documentation found

- `const MACON3_HFRMLEN = 0x04`

  No documentation found

- `const ECON1_TXRTS = 0x08`

  No documentation found

- `const PHCON1_PLOOPBK = 0x4000`

  No documentation found

- `const MACON3_PADCFG1 = 0x40`

  No documentation found

- `const PHIR = 0x13`

  No documentation found

- `const MICMD = (0x12|ENC_BANK_2|ENC_MIL)`

  No documentation found

- `const ESTAT_INT = 0x80`

      ENC28J60 ESTAT Register Bit Definitions

### Procedures

- `enc_clear_rx_buffer()`

      Clear entire rx buffer
      Needs work, I may be able to remove some lines.

- `enc_write_buffer(word in len)`

      write enc_array[] into the network buffer

- `enc_complete_packet_read()`

      complete packet read

- `enc_end_packet(word in network_current_packet_size)`

      End Packet/Send packet from transmit buffer onto twisted pair

- `enc_set_bank(byte in address)`

      Set bank number

- `enc_set_clkout_freq(byte in clk)`

  No documentation found

- `enc_write_phy_register(byte in address, word in data)`

      Write to a PHY register

- `enc_read_buffer(word in len)`

      read from the network buffer into enc_array[]

- `enc_init()`

  No documentation found

- `enc_spi_write_command(byte in operation, byte in address, byte in data)`

      Send write command to enc SPI interface

- `enc_write_register(byte in address, byte in data)`

      Write to a register

### Functions

- `enc_packet_size'get() return word`

      get the size of a packet (should only be read once at the
      beginning of a packet)

- `enc_read_revision() return byte`

      read the revision of the device

- `enc_packets_available() return byte`

      returns the number of packets currently available in the receive buffer

- `enc_packet_available'get() return bit`

      check if there are any packets available
      should only be read once before actually reading a packet

- `enc_spi_read_command(byte in operation, byte in address) return byte`

      Send read command to enc SPI interface

- `enc_read_register(byte in address) return byte`

      Read from a register

## Related samples

Here are the list of samples which use this library:

18f4620 | 18f4620_network_udp_server.jal
18f4620 | 18f4620_network_webserver_enc28j60.jal
18f4620 | 18f4620_network_udp_client.jal
18f4620 | 18f4620_network_all_in_one.jal
18f4620 | 18f4620_network_tcp_client.jal
18f4620 | 18f4620_network_tcp_server.jal
18f4620 | 18f4620_network_ping.jal