si5351a

Library for the Si5351a programmable any frequence clock generator.

Author Rob Jansen, Copyright © 2020..2020, all rights reserved.
Adapted-by
Compiler 2.5r4

Description

Libray for use of the Si5351a clock generator.


Sources

Inspired by the following sources:
         -) https://github.com/etherkit/Si5351Arduino
         -) https://radiotransmitter.wordpress.com/2017/02/23/a-simple-software-to-control-the-si5351a-generator-chip/
         -) https://www.rfzero.net/tutorials/si5351a/
         Application note AN619 from Silicon Labs. 


Notes

The following IIC pins must be defined by the main program before 
       including this library:
       -) alias si5351a_scl             -- To SCL of SI5351 
       -) alias si5351a_scl_direction    
       -) alias si5351a_sda             -- To SDA of SI5351       
       -) alias si5351a_sda_direction   


Dependencies

No dependency found



Summary

Global variables/contants

Procedures

Private

Functions

Private

API details

Global variables/contants

Procedures

Private
  • _store_multisynth_data(byte in start_register)

    Store the multisynth data available in the global array '_si5351a_ms_register_data'
    to the multisynth registers, starting at register 'start_register'.
    

  • _si5351a_update_all_clocks()

    Update all clocks with the current settings. This means re-calculating all 
    pll multisynth and output multisynth values and updating all registers. This
    function also assigns the clock source to the correct PLL.
    

  • _si5351a_write_register(byte in register, byte in data)

    Write a byte to the given Si5351a register via IIC.
    

  • _si5351a_calculate_pll_setting(dword in pll_frequency)

    Calculate the FMD divider. Note that we only use integer values so the PLL 
    freqency has to be set in steps of SI5351A_CRYSTAL_FREQUENCY.
    The Feedback Multisynth Divider (FMD) = a + (b/c) and since we use only
    integers (b=0) this makes calculation straight forward.
    The FMD ratio can be from 15 + 0/1048575 and to 90 + 0/1048575 which is 
    always the case for a PLL frequency between 600 MHz and 900 MHz and with a 
    crystal frequency of 25 MHz or 27 MHz.  
    The calculated values are stord in the global array _si5351a_ms_register_data
    


Functions

Private

Related samples

Here are the list of samples which use this library:

16f182516f1825_si5351a.jal
16f1885716f18857_si5351a.jal