pps

Peripheral Pin Select (PPS) library

Author Sebastion Lelong, Copyright © 2011..2021, All rights reserved.
Adapted-by Rob Hamerling, Rob Jansen, Oliver "Kiste" Seitz
Compiler 2.5r4

Description

This library supports Peripheral Pin Select of 3 major groups
of PICs, with significant differences in the PPS implementation:
   - 18F PICs with PPS (18FXXJ11, 18FXXJ13, 18FXXJ50, 18FXXJ53)
   - 18F PICs with PPS-light (high end PICs 18fxxj94/99)
   - Enhanced Midrange (16f15xx, 16f16xx, 16f17xx, 16f18xxx and lf variants).
Within these groups there are minor differences, such that we distinguish
5 PPS_GROUPS: PPS_1 for 18FxxJ11, 18FxxJ50
              PPS_2 for 18FxxJ13, 18FxxJ53
              PPS_3 for 18FxxJ94, 18FxxJ99
              PPS_4 for 16F16xx, 16f17xx (without PMD0 register)
              PPS_5 for 16F15xxx, 16f18xxx, 18FxxK40 (with PMD0 register)
The actual PPS-group is specified in the device file of each PIC
 (PPS_0 when the PIC has no PPS).
For all groups the basic rules with PPS are:
   * With OUTPUT a pin is assigned to a peripheral function
   * with INPUT the peripheral function is assigned to a pin.
.
Using PPS to (re-)configure a PIC involves 3 stages:
1. The PPS module must be unlocked with:
      pps_control_lock(FALSE)
2. Assign peripheral functions to specific pins.
   This stage is somewhat different for each of the major groups.
   PPS_1 and PPS_2:
      Example to (re)map pins TX2 and RX2 of the USART2 of a 18f27j53:
      To assign physical pin_B6 (alias pin_RP9) to the OUTPUT
      of the USART2 (TX2) specify:
            PPS_MAP_RP9 = PPS_TX2
      To assign INPUT of the USART2 (RX2) to physical pin_B7
      (alias RP10) specify:
            PPS_MAP_RX2 = RP10
   PPS_3:
      Not supported yet.
   PPS_4 and PPS_5:
      Example to (re)map pins TX and RX of the USART of a 16f1708:
      To assign physical pin_B7 to the OUTPUT of the USART (TX) specify:
            RC7PPS = PPS_TX
      To assign INPUT of the USART (RX) to physical pin_B6 specify:
            RXPPS = PPS_RB6
   For all PPS groups holds:
     -  Multiple peripheral functions can be mapped while the
        PPS module is unlocked.
     -  For bi-directional peripherals INPUT and OUTPUT must be
        mapped to the same physical pin.
3. Finally the PPS module must be locked with:
      pps_control_lock(TRUE).
.
When 1-way locking is used with:
  - for groups PPS_1, 2 and 3:   pragma fuse_def IOL1WAY ENABLED
  - for groups 4 and 5:          pragma fuse_def PPS1WAY ENABLED
peripheral pins can be assigned only once. When the PPS module is locked
again further changes are ignored (until reset or power-off).
This is the default behaviour of the PIC!
When more than one unlock/remap/lock sequence is required specify:
  for groups PPS_1, 2 and 3:  pragma fuse_def IOL1WAY DISABLED
  for groups PPS_4 and 5:     pragma fuse_def PPS1WAY DISABLED


Sources

Microchip TB3130 - Peripheral Pin Select in 8-Bit Microcontrollers Technical Brief
                   TB3098 - PIC16F170X Peripheral Pin Select (PPS) Technical Brief
                   Datasheets of the applicable PICs


Notes

- This library is the original PPS library by Sebastien Lelong for
         the 18Fs, extended by Rob Hamerling for the Enhanced Midrange.


Dependencies

No dependency found



Summary

Global variables/contants

Procedures

Functions


API details

Global variables/contants

Procedures

  • pps_control_lock(bit in state)

    Title:  Unlock/Lock the PPS module.
    Input:  Desired PPS lock state (bit: TRUE == locked, FALSE == unlocked)
    Returns: (nothing)
    Notes:  - Applies to all PPS-groups, differences are taken care of.
     Interrupts are disabled during the unlocked state.
    
    

Functions


Related samples

Here are the list of samples which use this library:

16f1532416f15324_pwm3_pwm4_led.jal
16f1532516f15325_adc.jal
16f1532516f15325_stopwatch2.jal
16f1532516f15325_stopwatch.jal
16f157916f1579_pwm3_16_bit_led.jal
16f157916f1579_pwm1_16_bit_led.jal
16f157916f1579_pwm4_16_bit_led.jal
16f157916f1579_pwm2_16_bit_led.jal
16f170816f1708_pps_serial_hw_int_cts.jal
16f177716f1777_pwm10_led.jal
16f177816f1778_pwm9_led.jal
16f177816f1778_pwm4_led.jal
16f177816f1778_pwm6_16_bit_led.jal
16f177816f1778_pwm3_led.jal
16f177816f1778_pwm5_16_bit_led.jal
16f177816f1778_pwm11_16_bit_led.jal
16f177916f1779_pwm12_16_bit_led.jal
16f1832316f18323_adc.jal
16f1832316f18323_pwm5_led.jal
16f1832316f18323_pwm6_led.jal
16f1885516f18855_pps_serial_hw_int_cts.jal
16f1885716f18857_touch_interrupt_ads7843.jal
16f1885716f18857_si5351a.jal
16f1885716f18857_glcd_ili9341_fat32_sd_card.jal
16f1885716f18857_philips_rc_decoder_serial.jal
16f1885716f18857_nec_rc_decoder_serial.jal
16f1885716f18857_glcd_ssd1306_font_graphics.jal
16f1885716f18857_glcd_ili9341.jal
16f1885716f18857_touch_ads7843.jal
16f1885716f18857_adc.jal
16f1917616f19176_serial_hardware.jal
16f1917616f19176_serial_hw2_int_cts.jal
16f1917616f19176_serial_hardware2.jal
16f1917616f19176_serial_hw_int_cts.jal
18f16q4018f16q40_serial_hardware3.jal
18f16q4018f16q40_serial_hw3_int_cts.jal
18f26j5018f26j50_sd_card.jal
18f26j5018f26j50_pps_rx2tx2.jal
18f26j5018f26j50_fat32_sd_card.jal
18f26k4218f26k42_serial_hardware.jal
18f26k4218f26k42_pwm7_led.jal
18f26k4218f26k42_serial_hardware2.jal
18f26k4218f26k42_pwm6_led.jal
18f26k4218f26k42_serial_hw_int_cts.jal
18f26k4218f26k42_pwm5_led.jal
18f26k4218f26k42_pwm8_led.jal
18f26k4218f26k42_serial_hw2_int_cts.jal
18f27j5318f27j53_pps_rx2tx2.jal
18f27j5318f27j53_xbee_api_rx.jal
18f27j5318f27j53_sd_card_minix_demo.jal
18f27j5318f27j53_sd_card_minix_read.jal
18f27j5318f27j53_sd_card_minix_readi.jal
18f46q1018f46q10_glcd_ili9341_font.jal
18f47q4318f47q43_serial_hardware2.jal
18f47q4318f47q43_serial_hardware.jal
18f47q4318f47q43_serial_hw_int_cts.jal
18f47q4318f47q43_serial_hw3_int_cts.jal
18f47q4318f47q43_serial_hw2_int_cts.jal
18f47q4318f47q43_serial_hardware3.jal